Cadence Hiring For 2024 | Design Engineer II | Apply Here !!

Responsibilities of the Candidate:

• Conduct pre-silicon emulation and verification of systems using NCSIM and Palladium.
• Design hardware and subsystems for all projects, including HW/SW infrastructure within the team.
• Develop prototypes and firmware for high-speed Serdes like PCIe, CXL, UCIe, USB, and Ethernet.
• Lead the bring-up, debug, compliance efforts, and system-level characterization until report release.
• Participate in interoperability testing and customer debug activities.
• Opportunity to work with cutting-edge SERDES IPs from Cadence, gaining expertise in SERDES PHY, controllers, protocol, and system integration.
• Demonstrate expertise in hardware and subsystem design.
• Deploy and debug solutions in different system environments.

Requirements:

• 1-3 years of experience (with B.Tech) or 0-2 years of experience (with M.Tech) in Post-Silicon PHY and Systems Validation.
• Experience in both physical layer and protocol layer on at least one high-speed SERDES.
• Strong debug skills and proficiency in using lab equipment such as oscilloscopes, bit error rate testers, protocol exercisers, and analyzers.
• Experience leading system validation efforts for SERDES solutions.
• Familiarity with PCIe LTSSM states is a plus.
• Experience in FPGA design and schematic design.
• Experience in IP/SoC physical layer electrical validation.
• Familiarity with Verilog RTL coding, FPGA coding, Python, and C/C++.
• Passion for analog and digital electronic circuit design.